The Circuit Design and Analysis of the Digital Delay-Lock Loop in GPS Receiver System
Vol. 19, No. 8, pp. 1464-1474, Aug. 1994
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Cite this article
[IEEE Style]
금홍식, 정은택, 이상곤, 권태환, 유흥균, "The Circuit Design and Analysis of the Digital Delay-Lock Loop in GPS Receiver System," The Journal of Korean Institute of Communications and Information Sciences, vol. 19, no. 8, pp. 1464-1474, 1994. DOI: .
[ACM Style]
금홍식, 정은택, 이상곤, 권태환, and 유흥균. 1994. The Circuit Design and Analysis of the Digital Delay-Lock Loop in GPS Receiver System. The Journal of Korean Institute of Communications and Information Sciences, 19, 8, (1994), 1464-1474. DOI: .
[KICS Style]
금홍식, 정은택, 이상곤, 권태환, 유흥균, "The Circuit Design and Analysis of the Digital Delay-Lock Loop in GPS Receiver System," The Journal of Korean Institute of Communications and Information Sciences, vol. 19, no. 8, pp. 1464-1474, 8. 1994.
pISSN : 1226 - 4717
eISSN : 2287 - 3880