FPGA Circuit Implementation of Despreading Delay Lock Loop for GPS Receiver and Performance Analysis
Vol. 22, No. 3, pp. 506-514, Mar. 1997
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Cite this article
[IEEE Style]
강성길 and 류흥균, "FPGA Circuit Implementation of Despreading Delay Lock Loop for GPS Receiver and Performance Analysis," The Journal of Korean Institute of Communications and Information Sciences, vol. 22, no. 3, pp. 506-514, 1997. DOI: .
[ACM Style]
강성길 and 류흥균. 1997. FPGA Circuit Implementation of Despreading Delay Lock Loop for GPS Receiver and Performance Analysis. The Journal of Korean Institute of Communications and Information Sciences, 22, 3, (1997), 506-514. DOI: .
[KICS Style]
강성길 and 류흥균, "FPGA Circuit Implementation of Despreading Delay Lock Loop for GPS Receiver and Performance Analysis," The Journal of Korean Institute of Communications and Information Sciences, vol. 22, no. 3, pp. 506-514, 3. 1997.
pISSN : 1226 - 4717
eISSN : 2287 - 3880