Design and Implementation of Acoustic Echo Canceller 


Vol. 29,  No. 2, pp. 291-297, Feb.  2004


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  Abstract

In this paper, a new structure for the AEC(Acoustic Echo Canceller) is proposed in which echo signal components that can be created in mobile communications is effectively eliminated. Block Data Flow Architecture is a parallel architecture that achieves high performance, high efficiency, high throughput, and almost linear speed up. The proposed architecture employs AEC and is implemented using the TMS320C6711 for real-time applications. The proposed AEC shows improved performance by eliminating echoes at 55ms delay path. Since the proposed AEC can also be implemented in Firmware, it is believed to effectively work on various types of echoes if it is applied on CDMA mobile devices. The TMS320C6711 shows much better performance comparing to previous DSPs.
For experimental verifications, filtering operation using adaptive algorithm is performed on TMS320C6711 board and error signals resulted from computations are monitored on PC, and then the performance of the implemented AEC is verified through ERLE computation. According the results of simulation, good characteristic of 100dB are shown after 500 sampling data.

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  Cite this article

[IEEE Style]

S. Jang and D. Moon, "Design and Implementation of Acoustic Echo Canceller," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 2, pp. 291-297, 2004. DOI: .

[ACM Style]

Su-An Jang and Dai-Tchul Moon. 2004. Design and Implementation of Acoustic Echo Canceller. The Journal of Korean Institute of Communications and Information Sciences, 29, 2, (2004), 291-297. DOI: .

[KICS Style]

Su-An Jang and Dai-Tchul Moon, "Design and Implementation of Acoustic Echo Canceller," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 2, pp. 291-297, 2. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880