A High-speed & Low power Design Technique for Open Loop 2-step ADC 


Vol. 29,  No. 4, pp. 439-446, Apr.  2004


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  Abstract

This paper describes high speed and low power design techniques for an 8-bit 500MSamples/s CMOS 2-step ADC. Instead of the conventional closed-loop architecture, the newly proposed ADC adopts open-loop architecture and uses a reset-switch to reduce loading time in an environment of big parasitic-capacitances of mux-array. An analog-latch is also used to reduce power consumption. Simulation result shows that the ADC has the SNDR of 46.91dB with a input frequency of 103MHz at 500Msample/s and consumes 203mW with a 1.8V single power supply. The chip is designed with a O.18㎛ 1-poly 6-metal CMOS technology and occupies active area of 760um*800um.

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  Cite this article

[IEEE Style]

S. Park, J. Koo, J. Youn, S. Lim, S. Kang, S. Kim, "A High-speed & Low power Design Technique for Open Loop 2-step ADC," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 4, pp. 439-446, 2004. DOI: .

[ACM Style]

Sunjae Park, Jahyun Koo, Jaeyoun Youn, Shin-Il Lim, Sung-Mo Kang, and Suki Kim. 2004. A High-speed & Low power Design Technique for Open Loop 2-step ADC. The Journal of Korean Institute of Communications and Information Sciences, 29, 4, (2004), 439-446. DOI: .

[KICS Style]

Sunjae Park, Jahyun Koo, Jaeyoun Youn, Shin-Il Lim, Sung-Mo Kang, Suki Kim, "A High-speed & Low power Design Technique for Open Loop 2-step ADC," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 4, pp. 439-446, 4. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880