Design of Frequency Synthesizer using Novel Architecture Programmable Frequency Divider 


Vol. 27,  No. 5, pp. 500-505, May  2002


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  Abstract

In this paper, a novel architecture of programmable divider with fifty percent duty cycle output and programmable dividing number has been proposed. Through HSPICE simulation, a 900㎒ frequency synthesizer with proposed frequency divider has designed in a standard 0.25㎛ CMOS technology. To verify the operation of proposed frequency divider, a chip had been fabricated using 0.65㎛ 2-poly, 3-metal standard CMOS processing and experimental result shows that the proposed frequency divider work well. The designed voltage controlled oscillator(VCO) has a center frequency of 900㎒ a tuning range of ±l0%, and a gain of l54㎒/V. The Simulated frequency synthesizer performance has a settling time of l.5㎲, a frequency range from 820㎒ to l㎓and power consumption of 70㎽ at 2.5V power supply voltage.

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  Cite this article

[IEEE Style]

T. Kim, S. Park, S. Son, "Design of Frequency Synthesizer using Novel Architecture Programmable Frequency Divider," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 5, pp. 500-505, 2002. DOI: .

[ACM Style]

Tae-Yob Kim, Soo-Yang Park, and Sang-Hee Son. 2002. Design of Frequency Synthesizer using Novel Architecture Programmable Frequency Divider. The Journal of Korean Institute of Communications and Information Sciences, 27, 5, (2002), 500-505. DOI: .

[KICS Style]

Tae-Yob Kim, Soo-Yang Park, Sang-Hee Son, "Design of Frequency Synthesizer using Novel Architecture Programmable Frequency Divider," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 5, pp. 500-505, 5. 2002.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880