A 8192-Point FFT Processor Based on the CORDIC Algorithm for OFDM System 


Vol. 27,  No. 8, pp. 787-795, Aug.  2002


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  Abstract

This paper presents the architecture and the implementation of a 2K/4K/8K-point complex Fast Fourier Transform (FFT) processor for Orthogonal Frequency-Division Multiplexing (OFDM) system. The architecture is based on the Cooley-Tukey algorithm for decomposing the long DFT into short length multi-dimensional DFTs. The transposition memory, shuffle memory, and memory mergence method are used for the efficient manipulation of data for multi-dimensional transforms. Booth algorithm and the COordinate Rotation DIgital Computer (CORDIC) processor are employed for the twiddle factor multiplications in each dimension. Also, for the CORDIC processor, a new twiddle factor generation method is proposed to obviate the ROM required for storing the twiddle factors. The overall 2K/4K/8K-FFT processor requires 600,000 gates, and it is implemented in 1.8 V 0.18 ㎛ CMOS. The processor can perform 8K-point FFT in every 273 ㎲, 2K-point every 68.26 ㎲ at 30M Hz, and the SNR is over 48dB, which are enough performances for the OFDM in DVB-T.

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  Cite this article

[IEEE Style]

S. Y. Park and N. I. Cho, "A 8192-Point FFT Processor Based on the CORDIC Algorithm for OFDM System," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 8, pp. 787-795, 2002. DOI: .

[ACM Style]

Sang Yoon Park and Nam Ik Cho. 2002. A 8192-Point FFT Processor Based on the CORDIC Algorithm for OFDM System. The Journal of Korean Institute of Communications and Information Sciences, 27, 8, (2002), 787-795. DOI: .

[KICS Style]

Sang Yoon Park and Nam Ik Cho, "A 8192-Point FFT Processor Based on the CORDIC Algorithm for OFDM System," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 8, pp. 787-795, 8. 2002.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880