Design of Hash Processor for SHA-1, HAS-160, and Pseudo-Random Number Generator 


Vol. 27,  No. 1, pp. 112-121, Jan.  2002


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  Abstract

In this paper, we present a design of a hash processor for data security systems. Two standard hash algorithms, SHA-1(American) and HAS-160(Korean), are implemented on a single hash engine to support real time processing of the algorithms. The hash processor can also be used as a PRNG(Pseudo-random number generator) by utilizing SHA-1 hash iterations, which is being used in the Intel software library. Because both SHA-l and HAS-160 have the same step operation, we could reduce hardware complexity by sharing the computation unit. Due to precomputation of message variables and two-stage pipelined structure, the critical path of the processor was shortened and overall performance was increased. We estimate performance of the hash processor about 624 Mbps for SHA-1 and HAS-160, and 195 Mbps for pseudo-random number generation, both at 100 MHz clock, based on Samsung 0.5um CMOS standard cell library. To our knowledge, this gives the best performance for processing the hash algorithms.

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  Cite this article

[IEEE Style]

S. Jeon, N. Kim, Y. Jeong, "Design of Hash Processor for SHA-1, HAS-160, and Pseudo-Random Number Generator," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 1, pp. 112-121, 2002. DOI: .

[ACM Style]

Shin-woo Jeon, Nam-young Kim, and Yong-jin Jeong. 2002. Design of Hash Processor for SHA-1, HAS-160, and Pseudo-Random Number Generator. The Journal of Korean Institute of Communications and Information Sciences, 27, 1, (2002), 112-121. DOI: .

[KICS Style]

Shin-woo Jeon, Nam-young Kim, Yong-jin Jeong, "Design of Hash Processor for SHA-1, HAS-160, and Pseudo-Random Number Generator," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 1, pp. 112-121, 1. 2002.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880