Design of SIMD-DSP/FPU for a Hih-Performance Embedded Microprocessor 


Vol. 27,  No. 4, pp. 388-397, Apr.  2002


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  Abstract

We designed a SIMD-DSP/FPU that can efficiently improve multimedia processing performance when integrated into high-performance embedded microprocessors. We proposed partitioned architectures and new schemes for several functional units to reduce chip area. Sharing functional units reduces the area of FPU significantly. The proposed architecture is modeled in HDL and synthesized with a 0.35um standard cell library. The chip area is estimated to be about 100,000 equivalent gates. The designed unit can run at higher than 50MHz clock frequency of CPU core under the worst-case operating conditions.

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  Cite this article

[IEEE Style]

W. Jeong, I. Hong, Y. Lee, Y. Lee, "Design of SIMD-DSP/FPU for a Hih-Performance Embedded Microprocessor," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 4, pp. 388-397, 2002. DOI: .

[ACM Style]

Woo-Kyeong Jeong, In-Pyo Hong, Yong-Joo Lee, and Yong-Surk Lee. 2002. Design of SIMD-DSP/FPU for a Hih-Performance Embedded Microprocessor. The Journal of Korean Institute of Communications and Information Sciences, 27, 4, (2002), 388-397. DOI: .

[KICS Style]

Woo-Kyeong Jeong, In-Pyo Hong, Yong-Joo Lee, Yong-Surk Lee, "Design of SIMD-DSP/FPU for a Hih-Performance Embedded Microprocessor," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 4, pp. 388-397, 4. 2002.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880