Low Power Force-Directed scheduling for Optimal module selection Architecture Synthesis 


Vol. 29,  No. 9, pp. 1091-1100, Sep.  2004


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  Abstract

In this paper, we present a reducing power conswnption of a scheduling for module selection under the time constraint.
The proposed low power scheduling executes FDS_LP considering low power to exist the FDS scheduling by inputted the behavioral language. The proposed FDS_LP perfonns lower power consumption with dynamic power which is minimized the switching activity, based on force conception In the time step of module selection, an optimal RT(Register Transfer) library is composed by exploration of the parameters such as power, area, and delay. To find optimal parameters of RT library, an optimal module selection algorithm using Branch and Bound algorithm is also proposed.
In the comparison and experimental results, The proposed FDS_LP algorithm reduce maximum power saving
up to 23.9% comparing to previous FDS algorithm

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  Cite this article

[IEEE Style]

J. Choi and H. Kim, "Low Power Force-Directed scheduling for Optimal module selection Architecture Synthesis," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 9, pp. 1091-1100, 2004. DOI: .

[ACM Style]

Ji-young Choi and Hi-seok Kim. 2004. Low Power Force-Directed scheduling for Optimal module selection Architecture Synthesis. The Journal of Korean Institute of Communications and Information Sciences, 29, 9, (2004), 1091-1100. DOI: .

[KICS Style]

Ji-young Choi and Hi-seok Kim, "Low Power Force-Directed scheduling for Optimal module selection Architecture Synthesis," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 9, pp. 1091-1100, 9. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880