Low-power FFT/IFFT Processor for Wireless LAN Modem 


Vol. 29,  No. 11, pp. 1263-1270, Nov.  2004


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  Abstract

A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAN modems. The radix-2/4/8 DIF (Decimation-In-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on internal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/lFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz@2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-㎲. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz@2.5-V.

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  Cite this article

[IEEE Style]

K. Shin, "Low-power FFT/IFFT Processor for Wireless LAN Modem," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 11, pp. 1263-1270, 2004. DOI: .

[ACM Style]

Kyung-Wook Shin. 2004. Low-power FFT/IFFT Processor for Wireless LAN Modem. The Journal of Korean Institute of Communications and Information Sciences, 29, 11, (2004), 1263-1270. DOI: .

[KICS Style]

Kyung-Wook Shin, "Low-power FFT/IFFT Processor for Wireless LAN Modem," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 11, pp. 1263-1270, 11. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880