Hardware Implementation of Fast Multi-resolution Motion Estimator for MPEG-4 AVC 


Vol. 29,  No. 11, pp. 1541-1550, Nov.  2004


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  Abstract

In this paper, we propose an advanced hardware architecture for fast multi-resolution motion estimation of the video coding standard MPEG-1,2 and MPEG-4 AVC. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and fast operation by using the shared memory, the special ram architecture, the motion vector for 4 pixel x 4 pixel, the spiral search and so on. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur Altera FPGA and also by ASIC synthesis using Samsung 0.18 um CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 140 MHz, processing more than 1,100 QCIF video frames or 70 4CIF video frames per second. The hardware is going to be used as a core module when implementing a complete MPEG-4 AVC video encoder ASIC for real-time multimedia application.

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  Cite this article

[IEEE Style]

Y. Lim and Y. Jeong, "Hardware Implementation of Fast Multi-resolution Motion Estimator for MPEG-4 AVC," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 11, pp. 1541-1550, 2004. DOI: .

[ACM Style]

Young-hun Lim and Yong-jin Jeong. 2004. Hardware Implementation of Fast Multi-resolution Motion Estimator for MPEG-4 AVC. The Journal of Korean Institute of Communications and Information Sciences, 29, 11, (2004), 1541-1550. DOI: .

[KICS Style]

Young-hun Lim and Yong-jin Jeong, "Hardware Implementation of Fast Multi-resolution Motion Estimator for MPEG-4 AVC," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 11, pp. 1541-1550, 11. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880