Hardware Implementation of a Fast Inter Prediction Engine for MPEG-4 AVC 


Vol. 30,  No. 3, pp. 102-111, Mar.  2005


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  Abstract

In this paper, we propose an advanced hardware architecture for the fast inter prediction engine of the video coding standard MPEG-4 AVC. We describe the algorithm and derive the hardware architecture emphasizing and real time operation of the quarter_pel based motion estimation. The fast inter prediction engine is composed of block segmentation, motion estimation, motion compensation, and the fast quarter_pel calculator. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur & Virtex2 FPGA, and also by synthesis on Samsung 0.18 um CMOS technology. The synthesis result shows that the proposed hardware can operate at 62.5MHz. In this case, it can process about 88 QCIF video frames per second. The hardware is being used as a core module when implementing a complete MPEG-4 AVC video encoder chip for real-time multimedia application.

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  Cite this article

[IEEE Style]

Y. h. Lim, D. j. Lee, Y. j. Jeong, "Hardware Implementation of a Fast Inter Prediction Engine for MPEG-4 AVC," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 3, pp. 102-111, 2005. DOI: .

[ACM Style]

Young hun Lim, Dae joon Lee, and Yong jin Jeong. 2005. Hardware Implementation of a Fast Inter Prediction Engine for MPEG-4 AVC. The Journal of Korean Institute of Communications and Information Sciences, 30, 3, (2005), 102-111. DOI: .

[KICS Style]

Young hun Lim, Dae joon Lee, Yong jin Jeong, "Hardware Implementation of a Fast Inter Prediction Engine for MPEG-4 AVC," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 3, pp. 102-111, 3. 2005.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880