An FPGA Design of High-Speed Turbo Decoder 


Vol. 30,  No. 6, pp. 450-456, Jun.  2005


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  Abstract

In this paper, we propose a high-speed turbo decoding algorithm and present results of its implementation. The latency caused by (de)interleaving and iterative decoding in conventional MAP turbo decoder can be dramatically reduced with the proposed scheme. The main cause of the time reduction is to use radix-4, center to top , and parallel decoding algorithm. The reduced latency makes it possible to use turbo decoder as a FEC scheme in the real-time wireless communication services. However the proposed scheme costs slight degradation in BER performance because the effective interleaver size in radix-4 is reduced to an half of that in conventional method. To ensure the time reduction, we implemented the proposed scheme on a FPGA chip and compared with conventional one in terms of decoding speed. The decoding speed of the proposed scheme is faster than conventional one at least by 5 times for a single iteration of turbo decoding.

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  Cite this article

[IEEE Style]

J. Jung, J. Jung, D. Choi, I. Lee, "An FPGA Design of High-Speed Turbo Decoder," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 6, pp. 450-456, 2005. DOI: .

[ACM Style]

Ji-Won Jung, Jin-Hee Jung, Duk-Gun Choi, and In-Ki Lee. 2005. An FPGA Design of High-Speed Turbo Decoder. The Journal of Korean Institute of Communications and Information Sciences, 30, 6, (2005), 450-456. DOI: .

[KICS Style]

Ji-Won Jung, Jin-Hee Jung, Duk-Gun Choi, In-Ki Lee, "An FPGA Design of High-Speed Turbo Decoder," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 6, pp. 450-456, 6. 2005.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880