Fixed-Width Booth-Folding Squarer Design 


Vol. 30,  No. 8, pp. 832-837, Aug.  2005


PDF
  Abstract

This paper presents a design method for fixed-width squarer that receives a W-bit input and produces a W-bit squared product. To efficiently compensate for the quantization error, modified Booth encoder signals (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups (major/minor group) depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulations, it is shown that the performance of the proposed method is close to that of the rounding method and much better than that of the truncation method and conventional method. It is also shown that the proposed method leads to up to 28% and 27% reduction in area and power consumption compared with the ideal squarers, respectively.

  Statistics
Cumulative Counts from November, 2022
Multiple requests among the same browser session are counted as one view. If you mouse over a chart, the values of data points will be shown.


  Cite this article

[IEEE Style]

K. Cho and J. Chung, "Fixed-Width Booth-Folding Squarer Design," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 8, pp. 832-837, 2005. DOI: .

[ACM Style]

Kyung-Ju Cho and Jin-Gyun Chung. 2005. Fixed-Width Booth-Folding Squarer Design. The Journal of Korean Institute of Communications and Information Sciences, 30, 8, (2005), 832-837. DOI: .

[KICS Style]

Kyung-Ju Cho and Jin-Gyun Chung, "Fixed-Width Booth-Folding Squarer Design," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 8, pp. 832-837, 8. 2005.

Search
(IN TITLE, AUTHOR, ABSTRACT,KEYWORDS)

Advanced Search ▼

POPULAR KEYWORDS
(TOP 10 KEYWORDS)

Recent Publications
(LAST 3 YEARS)






pISSN : 1226 - 4717
eISSN : 2287 - 3880