Design of Digital Codec for EPC RFID Protocols Generation 2 Class 1 Codec 


Vol. 31,  No. 3, pp. 360-367, Mar.  2006


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  Abstract

In this paper, we designed a digital codec of an RFID tag for EPC global generation 2 class 1. There are a large number of studies on RFID standard and anti-collision algorithm but few studies on the design of digital parts of the RFID　tag itself. For this reason, we studied and designed the digital codec hardware for EPC global generation 2 class 1 tag. The purpose of this paper is not to improve former studies but to present the hardware architecture, an estimation of hardware size and power consumption of digital part of the RFID tag. Results are synthesized using Synopsys with a 0.35um standard cell library. The hardware size is estimated to be 111640 equivalent inverters and dynamic power is estimated to be 10.4uW. It can be improved through full-custom design, but we designed using a standard cell library because it is faster and more efficient in the verification and the estimation of the design.

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  Cite this article

[IEEE Style]

Y. Lee, J. Jo, H. Kim, S. H. Kim, Y. Lee, "Design of Digital Codec for EPC RFID Protocols Generation 2 Class 1 Codec," The Journal of Korean Institute of Communications and Information Sciences, vol. 31, no. 3, pp. 360-367, 2006. DOI: .

[ACM Style]

Yong-joo Lee, Jung-hyeon Jo, Hyung-kyu Kim, Sang Hoon Kim, and Yong-Surk Lee. 2006. Design of Digital Codec for EPC RFID Protocols Generation 2 Class 1 Codec. The Journal of Korean Institute of Communications and Information Sciences, 31, 3, (2006), 360-367. DOI: .

[KICS Style]

Yong-joo Lee, Jung-hyeon Jo, Hyung-kyu Kim, Sang Hoon Kim, Yong-Surk Lee, "Design of Digital Codec for EPC RFID Protocols Generation 2 Class 1 Codec," The Journal of Korean Institute of Communications and Information Sciences, vol. 31, no. 3, pp. 360-367, 3. 2006.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880