Design and Implementation of Low-Power DCT Architecture by Minimizing Switching Activity 


Vol. 31,  No. 6, pp. 603-613, Jun.  2006


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  Abstract

Low-power design is one of the most important challenges encountered in maximizing battery life in portable devices as well as saving energy during system operation. In this paper we propose a low-power DCT (Discrete Cosine Transform) architecture using a modified Computation Sharing Multiplication (CSHM). The overall rate of power consumption is reduced during DCT: the proposed architecture does not perform arithmetic operations on unnecessary bits during the Computation Sharing Multiplication calculations. Experimental results show that it is possible to reduce power dissipation up to about 7~8% without compromising the final DCT results. The proposed low-power DCT architecture can be applied to consumer electronics as well as portable multimedia systems requiring high throughput and low-power.

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  Cite this article

[IEEE Style]

S. Kim, J. Park, Y. Lee, Y. Lee, "Design and Implementation of Low-Power DCT Architecture by Minimizing Switching Activity," The Journal of Korean Institute of Communications and Information Sciences, vol. 31, no. 6, pp. 603-613, 2006. DOI: .

[ACM Style]

San Kim, Jongsu Park, Yong-joo Lee, and Yong-Surk Lee. 2006. Design and Implementation of Low-Power DCT Architecture by Minimizing Switching Activity. The Journal of Korean Institute of Communications and Information Sciences, 31, 6, (2006), 603-613. DOI: .

[KICS Style]

San Kim, Jongsu Park, Yong-joo Lee, Yong-Surk Lee, "Design and Implementation of Low-Power DCT Architecture by Minimizing Switching Activity," The Journal of Korean Institute of Communications and Information Sciences, vol. 31, no. 6, pp. 603-613, 6. 2006.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880