FPGA Design of Turbo Code based on MAP 


Vol. 32,  No. 3, pp. 306-313, Mar.  2007


PDF Full-Text
  Abstract

In this paper, we efficiently implemented turbo code algorithm in FPGA H/W(hardware) resource. The used turbo code algorithm has the characteristics; the size of constraint is 3, encoder type is 1/3, the size of random interleaver is 2048. The proposed H/W consists of MAP block for calculating alpha and delta using delta value, storing buffer for each value, multiplier for calculating lamda, and lamda buffer. The proposed algorithm and H/W architecture was verified by C++ language and was designed by VHDL. Finally the designed H/W was programmed into FPGA and tested in wireless communication environment for field availability. The target FPGA of the implemented H/W is VERTEX4 XC4VFX12-12-SF363 and it is stably operated in 131.533㎒ clock frequency (7.603㎱).

  Statistics
Cumulative Counts from November, 2022
Multiple requests among the same browser session are counted as one view. If you mouse over a chart, the values of data points will be shown.


  Cite this article

[IEEE Style]

Y. Seo, "FPGA Design of Turbo Code based on MAP," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 3, pp. 306-313, 2007. DOI: .

[ACM Style]

Young-Ho Seo. 2007. FPGA Design of Turbo Code based on MAP. The Journal of Korean Institute of Communications and Information Sciences, 32, 3, (2007), 306-313. DOI: .

[KICS Style]

Young-Ho Seo, "FPGA Design of Turbo Code based on MAP," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 3, pp. 306-313, 3. 2007.

Search
(IN TITLE, AUTHOR, ABSTRACT,KEYWORDS)

Advanced Search ▼

POPULAR KEYWORDS
(TOP 10 KEYWORDS)

Recent Publications
(LAST 3 YEARS)






pISSN : 1226 - 4717
eISSN : 2287 - 3880