VLSI Implementation of Low-Power Motion Estimation Using Reduced Memory Accesses and Computations 


Vol. 32,  No. 5, pp. 503-509, May  2007


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  Abstract

Low-power motion estimation is required for video coding in portable information devices. In this paper, we propose a low-power motion estimation algorithm and 1-D systolic array VLSI architecture using full search block matching algorithm (FSBMA). Main power dissipation sources of FSBMA are complex computations and frequent memory accesses for data in the search area. In the proposed algorithm, memory accesses and computations are reduced by using 1D PE (processing array) array architecture performing motion estimation of two neighboring blocks in parallel and by skipping unnecessary computations during motion estimation. The VLSI implementation results of the algorithm show that the proposed VLSI architecture can save 9.3% power dissipation and can operate two times faster than an existing low-power motion estimator.

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  Cite this article

[IEEE Style]

J. Moon, N. Kim, J. Kim, W. Cho, "VLSI Implementation of Low-Power Motion Estimation Using Reduced Memory Accesses and Computations," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 5, pp. 503-509, 2007. DOI: .

[ACM Style]

Ji-Kyung Moon, Namsub Kim, Jinsang Kim, and Won-Kyung Cho. 2007. VLSI Implementation of Low-Power Motion Estimation Using Reduced Memory Accesses and Computations. The Journal of Korean Institute of Communications and Information Sciences, 32, 5, (2007), 503-509. DOI: .

[KICS Style]

Ji-Kyung Moon, Namsub Kim, Jinsang Kim, Won-Kyung Cho, "VLSI Implementation of Low-Power Motion Estimation Using Reduced Memory Accesses and Computations," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 5, pp. 503-509, 5. 2007.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880