VHDL Implementation of GEN2 Protocol for UHF RFID Tag 


Vol. 32,  No. 12, pp. 1311-1319, Dec.  2007


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  Abstract

This paper presents the VHDL implementation procedure of the passive RFID tag operating in Ultra High Frequency. The operation of the tag compatible with the EPCglobal Class1 Generation2(GEN2) protocol is verified by timing simulation after synthesis and implementation. Due to the reading range with relatively large distance, a passive tag needs digital processor which facilitates faster decoding, encoding and state transition for enhancement of an interrogation rate. In order to satisfy linking time, the pipe-line structure is used, which can minimize latency to serial input data stream. We also propose the sampling strategy to decode the Preamble, the Frame-sync and PIE symbols in reader commands. The simulation results with the fastest data rate and multi tags environment scenario show that the VHDL implemented tag performs faster operation than GEN2 proposed.

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  Cite this article

[IEEE Style]

I. S. Jang and H. G. Yang, "VHDL Implementation of GEN2 Protocol for UHF RFID Tag," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 12, pp. 1311-1319, 2007. DOI: .

[ACM Style]

Il Su Jang and Hoon Gee Yang. 2007. VHDL Implementation of GEN2 Protocol for UHF RFID Tag. The Journal of Korean Institute of Communications and Information Sciences, 32, 12, (2007), 1311-1319. DOI: .

[KICS Style]

Il Su Jang and Hoon Gee Yang, "VHDL Implementation of GEN2 Protocol for UHF RFID Tag," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 12, pp. 1311-1319, 12. 2007.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880