VLSI Architecture for Computer-Generated Hologram 


Vol. 33,  No. 7, pp. 540-547, Jul.  2008


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  Abstract

In this paper, we proposed a new VLSI architecture which can generate computer-generated hologram (CGH) in real-time and implemented to hardware. The modified algorithm for high-performance CGH was introduced and re-analyzed for designing hardware. From both numerical and visual analysis, the internal number system of hardware was decided. CGH algorithm and precision analysis enabled to propose a new cell architecture for CGH. The operational sequence was analyzed with the architecture of CGH cell and the characteristics of the modified CGH algorithm, and finally the pipelined architecture and the operational timing were proposed.

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  Cite this article

[IEEE Style]

Y. Seo, H. Choi, D. Kim, "VLSI Architecture for Computer-Generated Hologram," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 7, pp. 540-547, 2008. DOI: .

[ACM Style]

Young-Ho Seo, Hyun-Jun Choi, and Dong-Wook Kim. 2008. VLSI Architecture for Computer-Generated Hologram. The Journal of Korean Institute of Communications and Information Sciences, 33, 7, (2008), 540-547. DOI: .

[KICS Style]

Young-Ho Seo, Hyun-Jun Choi, Dong-Wook Kim, "VLSI Architecture for Computer-Generated Hologram," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 7, pp. 540-547, 7. 2008.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880