Digit-Parallel/Bit-Serial Multiplier for GF(2m) Using Polynomial Basis 


Vol. 33,  No. 11, pp. 892-897, Nov.  2008


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  Abstract

In this paper, a new architecture for digit-parallel/bit-serial GF(2m) multiplier with low latency is proposed. The proposed multiplier operates in polynomial basis of GF(2m) and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved.

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  Cite this article

[IEEE Style]

Y. Cho, "Digit-Parallel/Bit-Serial Multiplier for GF(2m) Using Polynomial Basis," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 11, pp. 892-897, 2008. DOI: .

[ACM Style]

Yong-suk Cho. 2008. Digit-Parallel/Bit-Serial Multiplier for GF(2m) Using Polynomial Basis. The Journal of Korean Institute of Communications and Information Sciences, 33, 11, (2008), 892-897. DOI: .

[KICS Style]

Yong-suk Cho, "Digit-Parallel/Bit-Serial Multiplier for GF(2m) Using Polynomial Basis," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 11, pp. 892-897, 11. 2008.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880