Design of monolithic DC-DC Buck converter with on chip soft-start circuit 


Vol. 34,  No. 7, pp. 568-573, Jul.  2009


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  Abstract

This paper presents a step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.13㎛ CMOS standard process. In an effort to decrease system volume, this paper proposes the on chip compensation circuit using capacitor multiplier method. Capacitor multiplier method can minimize error amplifier's compensation capacitor size by 10%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87.2% for the output voltage of 1.2V (input voltage : 3.3V), maximum load current 500㎃, and 25㎃ output ripple current. This voltage mode controled buck converter has 1㎒ switching frequency.

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  Cite this article

[IEEE Style]

S. Park, D. Lim, S. Lee, K. Yoon, "Design of monolithic DC-DC Buck converter with on chip soft-start circuit," The Journal of Korean Institute of Communications and Information Sciences, vol. 34, no. 7, pp. 568-573, 2009. DOI: .

[ACM Style]

Seung-chan Park, Dong-Kyun Lim, Sang-min Lee, and Kwang-sub Yoon. 2009. Design of monolithic DC-DC Buck converter with on chip soft-start circuit. The Journal of Korean Institute of Communications and Information Sciences, 34, 7, (2009), 568-573. DOI: .

[KICS Style]

Seung-chan Park, Dong-Kyun Lim, Sang-min Lee, Kwang-sub Yoon, "Design of monolithic DC-DC Buck converter with on chip soft-start circuit," The Journal of Korean Institute of Communications and Information Sciences, vol. 34, no. 7, pp. 568-573, 7. 2009.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880