Hardware Design for JBIG2 Encoder on Embedded System 


Vol. 35,  No. 2, pp. 182-192, Feb.  2010


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  Abstract

This paper proposes the hardware IP design of JBIG2 encoder. In order to facilitate the next generation FAX after the standardization of JBIG2, major modules of JBIG2 encoder are designed and implemented, such as symbol extraction module, Huffman coder, MMR coder, and MQ coder. ImpulseC Codeveloper and Xilinx ISE/EDK program are used for the synthesis of VHDL code. To minimize the memory usage, 128 lines of input image are processed succesively instead of total image. The synthesized IPs are downloaded to Virtex-4 FX60 FPGA on ML410 development board. The four synthesized IPs utilize 36.7% of total slice of FPGA. Using Active-HDL tool, the generated IPs were verified showing normal operation. Compared with the software operation using microblaze cpu on ML410 board, the synthesized IPs are better in operation time. The improvement ratio of operation time between the synthesized IP and software is 17 times in case of symbol extraction IP, and 10 times in Huffman coder IP. MMR coder IP shows 6 times faster and MQ coder IP shows 2.2 times faster than software only operation. The synthesized H/W IP and S/W module cooperated to succeed in compressing the CCITT standard document.

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  Cite this article

[IEEE Style]

S. Seo and H. Ko, "Hardware Design for JBIG2 Encoder on Embedded System," The Journal of Korean Institute of Communications and Information Sciences, vol. 35, no. 2, pp. 182-192, 2010. DOI: .

[ACM Style]

Seok-yong Seo and Hyung-Hwa Ko. 2010. Hardware Design for JBIG2 Encoder on Embedded System. The Journal of Korean Institute of Communications and Information Sciences, 35, 2, (2010), 182-192. DOI: .

[KICS Style]

Seok-yong Seo and Hyung-Hwa Ko, "Hardware Design for JBIG2 Encoder on Embedded System," The Journal of Korean Institute of Communications and Information Sciences, vol. 35, no. 2, pp. 182-192, 2. 2010.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880