Radiation-Induced Soft Error Detection Method for High Speed SRAM Instruction Cache 


Vol. 35,  No. 6, pp. 948-953, Jun.  2010


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  Abstract

In this paper, we propose multi-bit soft error detection method which can use an instruction cache of superscalar CPU architecture. Proposed method is applied to high-speed static RAM for instruction cache. Using 1D parity and interleaving, it has less memory overhead and detects more multi-bit errors comparing with other methods. It only detects occurrence of soft errors in static RAM. Error correction is treated like a cache miss situation. When soft errors are occurred, it is detected by 1D parity. Instruction cache just fetch the words from lower-level memory to correct errors. This method can detect multi-bit errors in maximum 4x4 window.

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  Cite this article

[IEEE Style]

S. Kwon, H. S. Choi, J. K. Park, J. T. Kim, "Radiation-Induced Soft Error Detection Method for High Speed SRAM Instruction Cache," The Journal of Korean Institute of Communications and Information Sciences, vol. 35, no. 6, pp. 948-953, 2010. DOI: .

[ACM Style]

Soongyu Kwon, Hyun Suk Choi, Jong Kang Park, and Jong Tae Kim. 2010. Radiation-Induced Soft Error Detection Method for High Speed SRAM Instruction Cache. The Journal of Korean Institute of Communications and Information Sciences, 35, 6, (2010), 948-953. DOI: .

[KICS Style]

Soongyu Kwon, Hyun Suk Choi, Jong Kang Park, Jong Tae Kim, "Radiation-Induced Soft Error Detection Method for High Speed SRAM Instruction Cache," The Journal of Korean Institute of Communications and Information Sciences, vol. 35, no. 6, pp. 948-953, 6. 2010.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880