Design and Verification of PCS Transmitting and Receiving Module for 40/100 Gigabit-Ethernet 


Vol. 35,  No. 11, pp. 1579-1587, Nov.  2010


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  Abstract

In this paper, we design the PCS(Physical Coding Sublayer) transmitting and receiving module for 40G/100G Ethernet and verify the performance of it through logic simulation. In this work, we defined each function module and internal/external control signals and implemented them using HDL programming language. We also designed 64B/66B encoding/decoding, scrambling/descrambling including operation mode, detection of invalid frames, and multi-lane based distribution/arrangement. It was simulated using ModelSim and verified in terms of the operation and timing according to input data. The simulation result shows that all designed modules in 40G/100G Ethernet are correctly performed.

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  Cite this article

[IEEE Style]

K. Han, S. Kim, K. Ahn, K. Kim, "Design and Verification of PCS Transmitting and Receiving Module for 40/100 Gigabit-Ethernet," The Journal of Korean Institute of Communications and Information Sciences, vol. 35, no. 11, pp. 1579-1587, 2010. DOI: .

[ACM Style]

Kyeong-Eun Han, Seung-Hwan Kim, Kye-hyun Ahn, and Kwangjoon Kim. 2010. Design and Verification of PCS Transmitting and Receiving Module for 40/100 Gigabit-Ethernet. The Journal of Korean Institute of Communications and Information Sciences, 35, 11, (2010), 1579-1587. DOI: .

[KICS Style]

Kyeong-Eun Han, Seung-Hwan Kim, Kye-hyun Ahn, Kwangjoon Kim, "Design and Verification of PCS Transmitting and Receiving Module for 40/100 Gigabit-Ethernet," The Journal of Korean Institute of Communications and Information Sciences, vol. 35, no. 11, pp. 1579-1587, 11. 2010.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880