FPGA-DSP Based Implementation of Lane and Vehicle Detection 


Vol. 36,  No. 12, pp. 727-737, Dec.  2011


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  Abstract

This paper presents an implementation scheme of real-time lane and vehicle detection system with FPGA and DSP. In this type of implementation, defining the functionality of each device in efficient manner is of crucial importance. The FPGA is in charge of extracting features from input image sequences in reduced form, and the features are provided to the DSP so that tracking lanes and vehicles are performed based on them. In addition, a way of seamless interconnection between those devices is presented. The experimental results show that the system is able to process at least 15 frames per second for video image sequences with size of 640 × 480.

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  Cite this article

[IEEE Style]

I. Kim and G. Kim, "FPGA-DSP Based Implementation of Lane and Vehicle Detection," The Journal of Korean Institute of Communications and Information Sciences, vol. 36, no. 12, pp. 727-737, 2011. DOI: .

[ACM Style]

Il-Ho Kim and Gyeonghwan Kim. 2011. FPGA-DSP Based Implementation of Lane and Vehicle Detection. The Journal of Korean Institute of Communications and Information Sciences, 36, 12, (2011), 727-737. DOI: .

[KICS Style]

Il-Ho Kim and Gyeonghwan Kim, "FPGA-DSP Based Implementation of Lane and Vehicle Detection," The Journal of Korean Institute of Communications and Information Sciences, vol. 36, no. 12, pp. 727-737, 12. 2011.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880