A New Low-Power Bus Encoding Scheme Using Bus-Invert Logic Conversion 


Vol. 36,  No. 12, pp. 1548-1555, Dec.  2011


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  Abstract

In ultra-deep submicron technology, minimization of propagation delay and power consumption on buses is one of the most important design objectives in system-on-chip (SOC) design. Crosstalk between adjacent wires on the bus may create a significant portion of propagation delay. Elimination or minimization of such faults is crucial to the performance and reliability of SOC designs. Most of the previous works on bus encoding are targeted either to minimize the bus switching or minimize the crosstalk delay, but not both. This paper proposes a new bus encoding scheme which can adaptively select one of functions “invert” and “logic-convert” according the number of bus switching on an encoded 4-bit cluster. This scheme leads to minimization of both crosstalk and bus switching. In experiment result, our proposed encoding technique consumes about 25% less power over the previous, while completely eliminating the crosstalk delay.

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  Cite this article

[IEEE Style]

Y. Lee, Q. Shidi, Y. Kim, "A New Low-Power Bus Encoding Scheme Using Bus-Invert Logic Conversion," The Journal of Korean Institute of Communications and Information Sciences, vol. 36, no. 12, pp. 1548-1555, 2011. DOI: .

[ACM Style]

Youn-Jin Lee, Qu Shidi, and Young-Chul Kim. 2011. A New Low-Power Bus Encoding Scheme Using Bus-Invert Logic Conversion. The Journal of Korean Institute of Communications and Information Sciences, 36, 12, (2011), 1548-1555. DOI: .

[KICS Style]

Youn-Jin Lee, Qu Shidi, Young-Chul Kim, "A New Low-Power Bus Encoding Scheme Using Bus-Invert Logic Conversion," The Journal of Korean Institute of Communications and Information Sciences, vol. 36, no. 12, pp. 1548-1555, 12. 2011.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880