Design of High Speed LDPC Encoder Based on DVB-S2 Standard 


Vol. 38,  No. 2, pp. 196-201, Feb.  2013


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  Abstract

In this paper, we proposed high speed LDPC encoder architecture for DVB-S2 standard. In conventional algorithm, the processes of parity calculations are serial fashion. Therefore conventional algorithm need clocks of number of parity .The proposed LDPC encoding architecture is based on a parallel 360 bits-wise operations. The key issues for realizing high speed are using the two kinds of index addresses and make use of memories efficiently. We implemented a half rate LDPC encoder on an FPGA, and confirmed its maximum throughput is up to 10 Gbps on 100MHz clock.

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  Cite this article

[IEEE Style]

G. Y. Park, S. R. Lee, S. M. Jeon, J. Jung, "Design of High Speed LDPC Encoder Based on DVB-S2 Standard," The Journal of Korean Institute of Communications and Information Sciences, vol. 38, no. 2, pp. 196-201, 2013. DOI: .

[ACM Style]

Gun Yeol Park, Seong Ro Lee, Sung Min Jeon, and Ji-Won Jung. 2013. Design of High Speed LDPC Encoder Based on DVB-S2 Standard. The Journal of Korean Institute of Communications and Information Sciences, 38, 2, (2013), 196-201. DOI: .

[KICS Style]

Gun Yeol Park, Seong Ro Lee, Sung Min Jeon, Ji-Won Jung, "Design of High Speed LDPC Encoder Based on DVB-S2 Standard," The Journal of Korean Institute of Communications and Information Sciences, vol. 38, no. 2, pp. 196-201, 2. 2013.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880