A Gigabit Serial Transceiver Design Using FPGA for Satellite Communication Transponder 


Vol. 39,  No. 8, pp. 481-487, Aug.  2014


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  Abstract

In this paper, we have proposed gigabit serial transceiver based on backplane architecture at the satellite communication digital transponder. The transponder supports the full combinational switching function with broadband multi-channel using programmable device - Xilinx space-grade Virtex-5 FPGA. In order to implement the switching function, GTX transceiver solution inside Virtex-5 FPGA is used. Also hardware implementation is simple because of no additional component. In order to use a GTX transceiver, signal integrity(SI) simulation of PCB design is essential. We investigate the characteristics of the S-parameter, eye diagram, channel jitter of GTX transmission line and conform that GTX Transceiver operates without error. Finally the proposed PCB design will be utilized at satellite communication digital transponder EQM-2(Engineering Qualification Model-2).

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  Cite this article

[IEEE Style]

K. Hong, J. Lee, B. Jin, H. Ko, H. Seo, "A Gigabit Serial Transceiver Design Using FPGA for Satellite Communication Transponder," The Journal of Korean Institute of Communications and Information Sciences, vol. 39, no. 8, pp. 481-487, 2014. DOI: .

[ACM Style]

Keun-Pyo Hong, Jung-Sub Lee, Byoung-Il Jin, Hyun-Suk Ko, and Hak-Geum Seo. 2014. A Gigabit Serial Transceiver Design Using FPGA for Satellite Communication Transponder. The Journal of Korean Institute of Communications and Information Sciences, 39, 8, (2014), 481-487. DOI: .

[KICS Style]

Keun-Pyo Hong, Jung-Sub Lee, Byoung-Il Jin, Hyun-Suk Ko, Hak-Geum Seo, "A Gigabit Serial Transceiver Design Using FPGA for Satellite Communication Transponder," The Journal of Korean Institute of Communications and Information Sciences, vol. 39, no. 8, pp. 481-487, 8. 2014.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880