Design of 6bit CMOS A/D Converter with Simplified S-R latch 


Vol. 33,  No. 11, pp. 963-969, Nov.  2008


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  Abstract

This paper presents 6bit 100㎒ Interpolation Flash Analog-to-Digital Converter, which can be applied to the Receiver of Wireless Tele-communication System. The 6bit 100㎒ Flash Analog-to-Digital Converter simplifies and integrates S-R latch which multiplies as the resolution increases. Whereas the conventional NAND based S-R latch needed eight MOS transistors, this Converter was designed with only six, which makes the Dynamic Power Dissipation of the A/D Converter reduced up to 12.5%. The designed A/D Converter went through 0.18㎛ CMOS n-well 1-poly 6-metal process to be a final product, and the final product has shown 282㎽ of power dissipation with 1.8V of Supply Voltage, 100㎒ of conversion rate. And 35.027㏈c, 31.253㏈ SFDR and 4.8bits, 4.2bits ENOB with 12.5㎒, 50㎒ of each input frequency.

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  Cite this article

[IEEE Style]

Y. Son, W. Kim, K. Yoon, "Design of 6bit CMOS A/D Converter with Simplified S-R latch," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 11, pp. 963-969, 2008. DOI: .

[ACM Style]

Young-jun Son, Won Kim, and Kwang-sub Yoon. 2008. Design of 6bit CMOS A/D Converter with Simplified S-R latch. The Journal of Korean Institute of Communications and Information Sciences, 33, 11, (2008), 963-969. DOI: .

[KICS Style]

Young-jun Son, Won Kim, Kwang-sub Yoon, "Design of 6bit CMOS A/D Converter with Simplified S-R latch," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 11, pp. 963-969, 11. 2008.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880