Low Complexity Digit-Parallel/Bit-Serial Polynomial Basis Multiplier 


Vol. 35,  No. 4, pp. 337-342, Apr.  2010


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  Abstract

In this paper, a new architecture for digit-parallel/bit-serial GF(2m) multiplier with low complexity is proposed. The proposed multiplier operates in polynomial basis of GF(2m) and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the digit-parallel/bit-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But the traditional digit-parallel/bit-serial multiplier needs extra hardware for high speed. In this paper a new low complexity efficient digit-parallel/bit-serial multiplier is presented.

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  Cite this article

[IEEE Style]

Y. Cho, "Low Complexity Digit-Parallel/Bit-Serial Polynomial Basis Multiplier," The Journal of Korean Institute of Communications and Information Sciences, vol. 35, no. 4, pp. 337-342, 2010. DOI: .

[ACM Style]

Yong-Suk Cho. 2010. Low Complexity Digit-Parallel/Bit-Serial Polynomial Basis Multiplier. The Journal of Korean Institute of Communications and Information Sciences, 35, 4, (2010), 337-342. DOI: .

[KICS Style]

Yong-Suk Cho, "Low Complexity Digit-Parallel/Bit-Serial Polynomial Basis Multiplier," The Journal of Korean Institute of Communications and Information Sciences, vol. 35, no. 4, pp. 337-342, 4. 2010.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880