Design of an Efficient Soft-Decision Demapper for Demodulator of DVB-S2 System 


Vol. 35,  No. 4, pp. 371-376, Apr.  2010


PDF Full-Text
  Abstract

This paper presents an efficient demapper architecture based soft-decision using the phase-section for Digital Video Broadcasting via satellite, Second Generation (DVB-S2). To achieve the satisfactory performance under a very low SNR conditions with the efficient hardware resource utilization, we propose a simple soft-decision demapper architecture using comparators to compare the phase of symbols and memories. The proposed architecture can decrease about 81% of the hardware resource, satisfying the BER requirements of DVB-S2. It has been thoroughly verified with an FPGA board and R&SⓡSFU (Rohde&Schwarz SFU-K108) broadcaast test equipment.

  Statistics
Cumulative Counts from November, 2022
Multiple requests among the same browser session are counted as one view. If you mouse over a chart, the values of data points will be shown.


  Cite this article

[IEEE Style]

C. D. Ryu and M. H. Sunwoo, "Design of an Efficient Soft-Decision Demapper for Demodulator of DVB-S2 System," The Journal of Korean Institute of Communications and Information Sciences, vol. 35, no. 4, pp. 371-376, 2010. DOI: .

[ACM Style]

Chang Duk Ryu and Myung Hoon Sunwoo. 2010. Design of an Efficient Soft-Decision Demapper for Demodulator of DVB-S2 System. The Journal of Korean Institute of Communications and Information Sciences, 35, 4, (2010), 371-376. DOI: .

[KICS Style]

Chang Duk Ryu and Myung Hoon Sunwoo, "Design of an Efficient Soft-Decision Demapper for Demodulator of DVB-S2 System," The Journal of Korean Institute of Communications and Information Sciences, vol. 35, no. 4, pp. 371-376, 4. 2010.

Search
(IN TITLE, AUTHOR, ABSTRACT,KEYWORDS)

Advanced Search ▼

POPULAR KEYWORDS
(TOP 10 KEYWORDS)

Recent Publications
(LAST 3 YEARS)






pISSN : 1226 - 4717
eISSN : 2287 - 3880