TY  - JOUR
T1  - SIMULINK Modeling and FPGA Implementation of Turbo Decoder for VDES Receiver
AU  - Kim, Jae Hyung 
JO  - The Journal of Korean Institute of Communications and Information Sciences
PY  - 2025
DA  - 2025/1/1
DO  - 10.7840/kics.2025.50.3.489
KW  - VDES
KW  - Turbo decoder
KW  - SIMULINK HDL compile
KW  - FILS
AB  - VDES(VHF Data Exchange System) defines the code rate, information length, interleaving, and puncturing methods for link ID 1~34, and is a digital maritime communication system that transmits large amounts of data at high speed based on various MCS (Modulation and Coding Schemes). In this paper, a Turbo decoder for VDES receivers is implemented in an FPGA. The Turbo decoder algorithm, which can support all link IDs of VDES, was modeled and verified using SIMULINK. The validated SIMULINK model was converted to Verilog by an HDL compiler, and the performance of the VDES Turbo decoder implemented in FPGA was tested using a VDES transmitter and receiver designed as a FPGA In the Loop Simulation test bench. The VDES must support encoding inputs with a maximum length of 6032 as well as various interleaving patterns depending on the link ID, so the Turbo decoder uses a sliding block with a length of 32 and a method of calculating the interleaving index in real time as a way to reduce memory usage. The designed VDES transceiver operates at a clock of 43.008 MHz and can complete demodulation and decoding within the VDES slot duration.